Semiconductor devices are manufactured by repeatedly performing a variety of processes such as a film-forming process, an etching process, etc. on a semiconductor wafer. According to recent demands for high speed of a semiconductor device, miniaturization of a wiring pattern, and high integration of a semiconductor device, a wiring requires an improvement in conductivity and resistance against electromigration.
In order to deal with this problem, copper (Cu) that has both higher conductivity (lower resistance) and better resistance to electromigration than aluminum (Al) or tungsten (W) has been used for wirings.
A method of forming a Cu wiring was proposed which includes forming a barrier film formed of tantalum (Ta), titanium (Ti), tantalum nitride (TaN), titanium nitride (TiN), or the like on the whole of an interlayer dielectric with a trench or a hole formed therein using a plasma sputtering apparatus as a PVD apparatus, forming a Cu seed film on the barrier film using the plasma sputtering apparatus, plating a Cu film on the Cu seed film to completely embed the trench or hole, and removing the extra Cu film on the surface of a wafer using chemical mechanical polishing (CMP) (e.g. Japanese Unexamined Patent Publication No. 2006-148075). Further, a technique of forming a Cu film that has good adhesion and can be formed on a micro fine pattern was also proposed which includes forming a Ru film on the barrier film using CVD, forming a Cu seed film, and forming a Cu plating film (e.g. Japanese Unexamined Patent Publication No. 2007-194624).
However, as design rules of semiconductor devices are gradually made finer, a width of a trench or a diameter of a hole amounts to tens nm. When the barrier film or the seed film is formed in the trench or the hole using the plasma sputtering apparatus, an overhang is generated in the opening of the trench or hole, so that even during subsequent Cu plating, the trench or hole is not completely filled with Cu, thereby creating voids.
For improved embedment, Japanese Unexamined Patent Publication No. 2006-148075 tried to control a bias power supplied to a loading stage of the plasma sputtering apparatus so as to regulate a film-forming rate and a sputtering-etching rate, or otherwise improve a Cu plating apparatus to increase embedment of Cu. Further, while the method disclosed in Japanese Unexamined Patent Publication No. 2007-194624 has higher embedment of Cu, it is difficult to adapt the method to a recently miniaturized trench or hole.
Further, since Cu plating has a great quantity of impurities, it cannot sufficiently deal with demand for lower resistance of a wiring.
Further, in case of using the plating, in addition to the PVD apparatus for forming the seed film, a plating apparatus is required, increasing both equipment costs and the number of processes, rendering the formation of the wiring complicated. Furthermore, since Cu plating has a large quantity of impurities, it cannot sufficiently deal with demand for lower resistance of a wiring. Thus, while it is expected that a Cu wiring is formed only using PVD without Cu plating, it is not as yet realized that a Cu wiring is formed in a narrow trench or hole in the magnitude of tens nm, only using PVD.